PZ3064AS7EC
EE PLD, 9ns, 64-Cell, CMOS, PBGA56Manufacturer: Xilinx
Categories: Programmable Logic Devices
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The Xilinx PZ3064AS7EC is a 64-cell EE PLD from the PZ3064 series, operating with a 3.3V nominal supply voltage (3.0V to 3.6V range). This device features a 9ns propagation delay and a maximum clock frequency of 111MHz. It is housed in a 56-terminal PBGA package (JESD-30 Code: S-PBGA-B56) with a 0.5mm terminal pitch, measuring 6x6mm with a seated height of 1.35mm. The organization includes 2 dedicated inputs and 44 I/O lines, supporting in-system programmability and JTAG boundary scan. This CMOS technology component is suitable for applications in industrial automation, consumer electronics, and telecommunications.
Additional Information
Series: PZ3064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 6.0000 |
| Width | 6.0000 |
| Technology | CMOS |
| Additional_Feature | Yes |
| Clock_Frequency_Max | 111.00000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PBGA-B56 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 2 |
| Number_of_I_O_Lines | 44 |
| Number_of_Macro_Cells | 64 |
| Number_of_Terminals | 56 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 2 DEDICATED INPUTS, 44 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | LFBGA |
| Package_Equivalence_Code | BGA56,10X10,20 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, LOW PROFILE, FINE PITCH |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 9.000 |
| Seated_Height_Max | 1.3500 |
| Supply_Voltage_Max | 3.60000 |
| Supply_Voltage_Min | 3.00000 |
| Supply_Voltage_Nom | 3.3 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 0.500 |
| Terminal_Position | Bottom |
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