TBP24SA81-55JP4
OTP ROM, 1KX8, 50ns, TTL, CDIP18Manufacturer: Texas Instruments
Categories: OTP ROMs
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The Texas Instruments TBP24SA81-55JP4 is an OTP ROM featuring a memory organization of 1K x 8 with a total density of 8192 bits. This asynchronous memory component operates with a maximum access time of 50 ns and utilizes TTL technology. Designed for through-hole mounting, it is housed in an 18-lead ceramic dual in-line package (CDIP18) with a terminal pitch of 2.54 mm. The TBP24SA81 series component is rated for an operating temperature range of 0°C to 70°C and typically operates at a 5V supply voltage. This device finds application in various industrial and consumer electronics systems requiring non-volatile program storage.
Additional Information
Series: TBP24SA81RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Technology | TTL |
| Access_Time_Max | 50.0000000000000000 |
| JESD_30_Code | R-XDIP-T18 |
| Memory_Density | 8192.0000000000000000 |
| Memory_IC_Type | OTP ROM |
| Memory_Organization | 1KX8 |
| Memory_Width | 8 |
| Number_of_Functions | 1 |
| Number_of_Terminals | 18 |
| Number_of_Words | 2048.0000000000000000 |
| Number_of_Words_Code | 1k |
| Operating_Mode | Asynchronous |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Package_Body_Material | Ceramic |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP18,.3 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Parallel_Serial | Parallel |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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