TBP24SA81-55J4
OTP ROM, 32KX8, 45ns, TTL, CDIP18Manufacturer: Texas Instruments
Categories: OTP ROMs
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Texas Instruments TBP24SA81-55J4 is a 32K x 8 bit One-Time Programmable (OTP) Read-Only Memory (ROM) component. Featuring a maximum access time of 45ns, this device operates with TTL compatible logic levels. The memory organization is 32K words by 8 bits, providing a total memory density of 262,144 bits. This asynchronous memory operates from a nominal supply voltage of 5V. The TBP24SA81-55J4 is housed in a CDIP18 (Ceramic Dual In-line Package) with 18 through-hole terminals on a 2.54mm pitch. This component finds application in systems requiring non-volatile program storage and data retention, often utilized in industrial control and legacy system designs. The operating temperature range is from 0°C to 70°C.
Additional Information
Series: TBP24SA81RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Technology | TTL |
| Access_Time_Max | 45.0000000000000000 |
| JESD_30_Code | R-XDIP-T18 |
| Memory_Density | 262144.0000000000000000 |
| Memory_IC_Type | OTP ROM |
| Memory_Organization | 32KX8 |
| Memory_Width | 8 |
| Number_of_Functions | 1 |
| Number_of_Terminals | 18 |
| Number_of_Words | 2048.0000000000000000 |
| Number_of_Words_Code | 32k |
| Operating_Mode | Asynchronous |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Package_Body_Material | Ceramic |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP18,.3 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Parallel_Serial | Parallel |
| Supply_Current_Max | 30.000000000000000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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