TMS4C1025-12DJL
Nibble Mode DRAM, 1MX1, 120ns, CMOS, PDSO20Manufacturer: Texas Instruments
Categories: DRAMs
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Texas Instruments TMS4C1025-12DJL is a 1 Mbit CMOS Nibble Mode DRAM with a 1M x 1 organization. This component features a maximum access time of 120ns and operates asynchronously. Supported refresh modes include RAS ONLY, CAS BEFORE RAS, and HIDDEN REFRESH, with 512 refresh cycles required. The device utilizes a PDSO20 (SOJ) package, a JEDEC standard R-PDSO-J20, designed for surface mounting with a 1.27mm terminal pitch. Key specifications include a supply voltage range of 4.5V to 5.5V with a nominal 5V, and an operating temperature range of 0°C to 70°C. This DRAM is suitable for applications in industrial control, consumer electronics, and telecommunications systems requiring high-speed memory access.
Additional Information
Series: TMS4C1025RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 17.1450 |
| Width | 7.5700 |
| Technology | CMOS |
| Access_Mode | NIBBLE |
| Access_Time_Max | 120.0000000000000000 |
| Additional_Feature | RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH |
| JESD_30_Code | R-PDSO-J20 |
| Memory_Density | 1048576.0000000000000000 |
| Memory_IC_Type | NIBBLE MODE DRAM |
| Memory_Organization | 1MX1 |
| Memory_Width | 1 |
| Number_of_Functions | 1 |
| Number_of_Ports | 1 |
| Number_of_Terminals | 20 |
| Number_of_Words | 1048576.0000000000000000 |
| Number_of_Words_Code | 1M |
| Operating_Mode | Asynchronous |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Output_Characteristics | 3-State |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | SOJ |
| Package_Shape | Rectangular |
| Package_Style | SMALL OUTLINE |
| Refresh_Cycles | 512 |
| Seated_Height_Max | 3.7600 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | Dual |
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