P3C18V8ZIN
OT PLD, 50ns, CMOS, PDIP20Manufacturer: NXP Semiconductors
Categories: Programmable Logic Devices
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NXP Semiconductors P3C18V8ZIN is an 8-macrocell, CMOS, OT PLD featuring register preload, power-up reset, and support for one external clock. This device offers 8 dedicated inputs and 8 I/O lines with a maximum clock frequency of 17 MHz. The propagation delay is rated at 50 ns. Designed for through-hole mounting, it utilizes a 20-pin PDIP package (R-PDIP-T20) with a terminal pitch of 2.54 mm. Operating within a temperature range of -40°C to 85°C, the P3C18V8ZIN supports a supply voltage range of 2.7V to 3.6V, with a nominal voltage of 3.3V. This component finds application in industrial automation and consumer electronics.
Additional Information
Series: P3C18V8RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 26.7300 |
| Width | 7.6200 |
| Technology | CMOS |
| Additional_Feature | 8 MACROCELLS; REGISTER PRELOAD; POWER-UP RESET; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| Clock_Frequency_Max | 17.00000 |
| JESD_30_Code | R-PDIP-T20 |
| Number_of_Dedicated_Inputs | 8 |
| Number_of_I_O_Lines | 8 |
| Number_of_Terminals | 20 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 8 DEDICATED INPUTS, 8 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP20,.3 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 50.000 |
| Seated_Height_Max | 4.2000 |
| Supply_Voltage_Max | 3.60000 |
| Supply_Voltage_Min | 2.70000 |
| Supply_Voltage_Nom | 3.3 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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