LPC1830FET100
RISC Microcontroller, 32-Bit, FLASH, 180MHz, CMOS, PBGA100Manufacturer: NXP Semiconductors
Categories: Microcontrollers
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The NXP Semiconductors LPC1830FET100 is a 32-bit ARM Cortex-M3 based RISC microcontroller operating at speeds up to 180MHz. This device features 1MB of Flash program memory and 160KB of SRAM, supporting a 24-bit address bus. It includes a comprehensive peripheral set, such as multiple SPI, I2S, and UART interfaces, along with an 8-channel 12-bit ADC and two 10-bit DACs. The LPC1830FET100 also offers extensive I/O capabilities with 49 general-purpose I/O lines and multiple DMA channels for efficient data transfer. Packaged in a 100-pin TFBGA (JESD-30 Code: S-PBGA-B100) with a 0.80mm terminal pitch, it operates within a temperature range of -40°C to +85°C and supports a supply voltage from 2.2V to 3.6V. Applications span industrial automation, motor control, and high-performance embedded systems.
Additional Information
Series: LPC1830RoHS Status: RoHS CompliantManufacturer Lead Time: Product Status: ActivePackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 9.0000 |
| Speed | 180.00000000 |
| Width | 9.0000 |
| Technology | CMOS |
| ADC_Channels | Yes |
| Address_Bus_Width | 24 |
| Bit_Size | 32 |
| Clock_Frequency_Max | 25.0000000000000000 |
| DAC_Channels | Yes |
| DMA_Channels | Yes |
| External_Data_Bus_Width | 32 |
| JESD_30_Code | S-PBGA-B100 |
| Number_of_I_O_Lines | 49 |
| Number_of_Terminals | 100 |
| Operating_Temperature_Max | 85.0000 |
| Operating_Temperature_Min | -40.0000 |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | TFBGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, THIN PROFILE, FINE PITCH |
| Program_Memory_Type | FLASH |
| PWM_Channels | No |
| Seated_Height_Max | 1.2000 |
| Supply_Voltage_Max | 3.6000 |
| Supply_Voltage_Min | 2.2000 |
| Supply_Voltage_Nom | 3.3000 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 0.800 |
| Terminal_Position | Bottom |
| uPs_uCs_Peripheral_ICs_Type | MICROCONTROLLER, RISC |
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