LPC11E14FHN33/401
RISC Microcontroller, 32-Bit, FLASH, CORTEX-M0 CPU, 50MHz, CMOS, PQCC33Manufacturer: NXP Semiconductors
Categories: Microcontrollers
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NXP Semiconductors LPC11E14FHN33-401 is a 32-bit RISC microcontroller featuring an ARM Cortex-M0 CPU operating at up to 50MHz. This CMOS device offers 32KB of FLASH program memory and 4KB of data RAM. It includes 28 general-purpose I/O lines and supports boundary scan functionality. Designed for surface-mount applications, it utilizes a 33-terminal PQCC33 package with a 0.65mm terminal pitch. The operating temperature range is -40°C to +85°C, with a nominal supply voltage of 3.3V. This component is suitable for applications in industrial automation, consumer electronics, and medical devices.
Additional Information
Series: LPC11E14RoHS Status: RoHS CompliantManufacturer Lead Time: Product Status: ActivePackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 7.0000 |
| Speed | 50.00000000 |
| Width | 7.0000 |
| Technology | CMOS |
| ADC_Channels | Yes |
| Address_Bus_Width | 0 |
| Bit_Size | 32 |
| Boundary_Scan | Yes |
| Clock_Frequency_Max | 25.0000000000000000 |
| CPU_Family | CORTEX-M0 |
| DAC_Channels | No |
| Data_RAM_Size | 4096 |
| DMA_Channels | No |
| External_Data_Bus_Width | 0 |
| JESD_30_Code | S-PQCC-N33 |
| Number_of_I_O_Lines | 28 |
| Number_of_Terminals | 33 |
| Operating_Temperature_Max | 85.0000 |
| Operating_Temperature_Min | -40.0000 |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | HVQCCN |
| Package_Equivalence_Code | LCC32,.27SQ,25 |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE |
| Program_Memory_Size | 32768 |
| Program_Memory_Type | FLASH |
| Program_Memory_Width | 8 |
| PWM_Channels | No |
| Seated_Height_Max | 1.0000 |
| Supply_Voltage_Max | 3.6000 |
| Supply_Voltage_Min | 3.3000 |
| Supply_Voltage_Nom | 3.3000 |
| Surface_Mount | Yes |
| Terminal_Form | NO LEAD |
| Terminal_Pitch | 0.650 |
| Terminal_Position | QUAD |
| uPs_uCs_Peripheral_ICs_Type | MICROCONTROLLER, RISC |
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