MCM5L4100AN70
Fast Page DRAM, 4MX1, 70ns, CMOS, PDSO20Manufacturer: NXP Semiconductors
Categories: DRAMs
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NXP Semiconductors MCM5L4100AN70 is a 4M x 1 Fast Page DRAM component, offering a memory density of 4,194,304 bits. This CMOS device features a maximum access time of 70ns, utilizing separate I/O. The MCM5L4100AN70 is housed in a 20-terminal SOJ package (R-PDSO-J20) with a terminal pitch of 1.27mm, designed for surface mounting. Operating within a temperature range of 0°C to 70°C, it requires a nominal supply voltage of 5V. This component is suitable for applications in consumer electronics, industrial control, and telecommunications systems. The memory organization is 4M words by 1 bit, with a refresh cycle requirement of 1024. The output characteristics are 3-state.
Additional Information
Series: MCM5L4100RoHS Status: Manufacturer Lead Time: Product Status: Active-UnconfirmedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Technology | CMOS |
| Access_Time_Max | 70.0000000000000000 |
| I_O_Type | SEPARATE |
| JESD_30_Code | R-PDSO-J20 |
| Memory_Density | 4194304.0000000000000000 |
| Memory_IC_Type | FAST PAGE DRAM |
| Memory_Organization | 4MX1 |
| Memory_Width | 1 |
| Number_of_Terminals | 20 |
| Number_of_Words | 4194304.0000000000000000 |
| Number_of_Words_Code | 4M |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Output_Characteristics | 3-State |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | SOJ |
| Package_Equivalence_Code | SOJ20/26,.34 |
| Package_Shape | Rectangular |
| Package_Style | SMALL OUTLINE |
| Refresh_Cycles | 1024 |
| Self_Refresh | No |
| Standby_Current_Max | 0.000200000000000 |
| Supply_Current_Max | 100.000000000000000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | Dual |
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