WEDMC64603RV200CM
RISC Microprocessor, 32-Bit, 200MHz, CMOS, CBGA255Manufacturer: Microsemi Corporation
Categories: Microprocessors
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The Microsemi Corporation WEDMC64603RV200CM is a 32-bit RISC microprocessor operating at a maximum clock frequency of 200MHz. This CMOS component, manufactured by Microsemi Corporation under the WEDMC64603 series, features a 255-pin CBGA (Ceramic Grid Array) package with a terminal pitch of 1.270mm. Key specifications include a 32-bit address and external data bus width, support for boundary scan, and low-power modes. The device requires a PLL supply voltage between 2.375V and 2.625V, with a nominal 2.50V, and an I/O supply voltage ranging from 3.135V to 3.465V. It operates across an extended temperature range of -55°C to 125°C. This microprocessor is suitable for applications in aerospace and defense, and industrial automation.
Additional Information
Series: WEDMC64603RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Format | Floating Point |
| Speed | 200.00000000 |
| Width | 21.0000 |
| Technology | CMOS |
| Length | 21.0000 |
| Additional_Feature | IC ALSO REQUIRES PLL SUPPLY VOLTAGE OF 2.375V TO 2.625V AND I/O SUPPLY VOLTAGE OF 3.135V TO 3.465V |
| Address_Bus_Width | 32 |
| Bit_Size | 32 |
| Boundary_Scan | Yes |
| Clock_Frequency_Max | 200.0000000000000000 |
| External_Data_Bus_Width | 32 |
| Integrated_Cache | No |
| JESD_30_Code | S-CBGA-C255 |
| Low_Power_Mode | Yes |
| Number_of_Terminals | 255 |
| Operating_Temperature_Max | 125.0000 |
| Operating_Temperature_Min | -55.0000 |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | CGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Seated_Height_Max | 4.4000 |
| Supply_Voltage_Max | 2.6250 |
| Supply_Voltage_Min | 2.3750 |
| Supply_Voltage_Nom | 2.5000 |
| Surface_Mount | Yes |
| Terminal_Form | C BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | Bottom |
| uPs_uCs_Peripheral_ICs_Type | MICROPROCESSOR, RISC |
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