DP51C68-35L
Standard SRAM, 4KX4, 35ns, CMOS, CDIP20Manufacturer: Intel
Categories: SRAMs
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Intel DP51C68-35L is a 4K x 4 CMOS Standard SRAM with a maximum access time of 35ns. This asynchronous memory component features automatic power-down and 3-state outputs. Organized as 4,096 words with a 4-bit data width, it operates with a supply voltage range of 4.5V to 5.5V. The DP51C68-35L is housed in a 20-pin Ceramic Dual In-line Package (CDIP) with through-hole mounting. Its specifications make it suitable for applications in industrial and consumer electronics requiring reliable, moderate-speed data storage.
Additional Information
Series: DP51C68RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.8250 |
| Width | 7.6200 |
| Technology | CMOS |
| Access_Time_Max | 35.0000000000000000 |
| Additional_Feature | AUTOMATIC POWER-DOWN |
| JESD_30_Code | R-GDIP-T20 |
| Memory_Density | 16384.0000000000000000 |
| Memory_IC_Type | STANDARD SRAM |
| Memory_Organization | 4KX4 |
| Memory_Width | 4 |
| Number_of_Functions | 1 |
| Number_of_Ports | 1 |
| Number_of_Terminals | 20 |
| Number_of_Words | 4096.0000000000000000 |
| Number_of_Words_Code | 4k |
| Operating_Mode | Asynchronous |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Output_Characteristics | 3-State |
| Output_Enable | No |
| Package_Body_Material | CERAMIC, GLASS-SEALED |
| Package_Code | DIP |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Parallel_Serial | Parallel |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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