DP51C68-30
Standard SRAM, 4KX4, 30ns, CMOS, CDIP20Manufacturer: Intel
Categories: SRAMs
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The Intel DP51C68-30 is a standard asynchronous CMOS SRAM with a memory organization of 4K words by 4 bits, providing a total density of 16Kb. This component features a maximum access time of 30ns and operates with a supply voltage range of 4.5V to 5.5V, with a nominal voltage of 5V. Designed for through-hole mounting, it is housed in a 20-lead Ceramic DIP (CDIP) package (JESD-30 Code: R-GDIP-T20) with a terminal pitch of 2.54mm. Key operational characteristics include automatic power-down functionality and 3-state outputs. This device is suitable for applications in industrial control, telecommunications infrastructure, and consumer electronics requiring reliable, static memory.
Additional Information
Series: DP51C68RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.8250 |
| Width | 7.6200 |
| Technology | CMOS |
| Access_Time_Max | 30.0000000000000000 |
| Additional_Feature | AUTOMATIC POWER-DOWN |
| JESD_30_Code | R-GDIP-T20 |
| Memory_Density | 16384.0000000000000000 |
| Memory_IC_Type | STANDARD SRAM |
| Memory_Organization | 4KX4 |
| Memory_Width | 4 |
| Number_of_Functions | 1 |
| Number_of_Ports | 1 |
| Number_of_Terminals | 20 |
| Number_of_Words | 4096.0000000000000000 |
| Number_of_Words_Code | 4k |
| Operating_Mode | Asynchronous |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Output_Characteristics | 3-State |
| Output_Enable | No |
| Package_Body_Material | CERAMIC, GLASS-SEALED |
| Package_Code | DIP |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Parallel_Serial | Parallel |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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