EPM9560GI280-20
EE PLD, 23.6ns, 560-Cell, CMOS, CPGA280Manufacturer: Intel
Categories: Programmable Logic Devices
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The Intel EPM9560GI280-20 is a high-density EE PLD from the EPM9560 series. This CMOS device features 560 macrocells and 216 I/O lines, offering 772 flip-flops for complex logic implementation. It supports configurable I/O operation at 3.3V or 5V, with a maximum clock frequency of 100MHz. The propagation delay is 23.6ns. This in-system programmable device utilizes a 280-pin Ceramic Pin Grid Array (CPGA) package with a terminal pitch of 2.54mm. Operating within a temperature range of -40°C to 85°C, it is suitable for applications in industrial, communications, and consumer electronics sectors. The EPM9560GI280-20 includes JTAG Boundary Scan (BST) for efficient testing.
Additional Information
Series: EPM9560RoHS Status: Manufacturer Lead Time: Product Status: ActivePackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 49.7800 |
| Width | 49.7800 |
| Technology | CMOS |
| Additional_Feature | 772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 100.00000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-CPGA-P280 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 216 |
| Number_of_Macro_Cells | 560 |
| Number_of_Terminals | 280 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 0 DEDICATED INPUTS, 216 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA280,19X19 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 23.600 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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