EPM7256EGI192-12
EE PLD, 12ns, 256-Cell, CMOS, CPGA192Manufacturer: Intel
Categories: Programmable Logic Devices
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The Intel EPM7256EGI192-12 is a high-performance EE PLD from the EPM7256 series, featuring 256 macrocells and a maximum clock frequency of 125 MHz. This CMOS device offers a propagation delay of 12 ns and supports 164 I/O lines. It is housed in a 192-terminal Ceramic Pin Grid Array (CPGA) package with a terminal pitch of 2.54 mm, designed for robust operation between -40°C and 85°C. The component operates with a nominal supply voltage of 5V, with a range of 4.5V to 5.5V. This device finds application in telecommunications, industrial control, and consumer electronics requiring flexible, high-speed logic solutions.
Additional Information
Series: EPM7256RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 45.1500 |
| Width | 45.1500 |
| Technology | CMOS |
| Additional_Feature | 256 MACROCELLS |
| Clock_Frequency_Max | 125.00000 |
| In_System_Programmable | No |
| JESD_30_Code | S-CPGA-P192 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 164 |
| Number_of_Inputs | 164 |
| Number_of_Macro_Cells | 256 |
| Number_of_Outputs | 164 |
| Number_of_Terminals | 192 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 0 DEDICATED INPUTS, 164 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA192M,17X17 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 12.000 |
| Seated_Height_Max | 5.4300 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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