DPLD910-25
UV PLD, 28ns, PAL-Type, CMOS, CDIP40Manufacturer: Intel
Categories: Programmable Logic Devices
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Intel DPLD910-25 is a UV Programmable Logic Device from the DPLD910 series, featuring a PAL-type architecture. This CMOS device offers 24 macrocells with 2 external clock inputs and supports asynchronous clocking. It boasts 36 total inputs, including 12 dedicated inputs, and 24 I/O lines. The device provides 240 product terms and a maximum clock frequency of 27.7 MHz, with a typical propagation delay of 28 ns. Operating within a 4.75V to 5.25V supply range, the DPLD910-25 is housed in a 40-lead ceramic dual in-line package (CDIP40) with a through-hole terminal form. This component is suitable for applications in industrial control and telecommunications.
Additional Information
Series: DPLD910RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 52.3250 |
| Width | 15.2400 |
| Technology | CMOS |
| Architecture | PAL-TYPE |
| Additional_Feature | PAL WITH MACROCELLS; 24 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS |
| Clock_Frequency_Max | 27.70000 |
| JESD_30_Code | R-GDIP-T40 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 24 |
| Number_of_Inputs | 36 |
| Number_of_Outputs | 24 |
| Number_of_Product_Terms | 240 |
| Number_of_Terminals | 40 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 24 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, GLASS-SEALED |
| Package_Code | WDIP |
| Package_Equivalence_Code | DIP40,.6 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE, WINDOW |
| Programmable_Logic_Type | UV PLD |
| Propagation_Delay | 28.000 |
| Seated_Height_Max | 5.7200 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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