DPLD610-25
UV PLD, 25ns, PAL-Type, CMOS, CDIP24Manufacturer: Intel
Categories: Programmable Logic Devices
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Intel DPLD610-25 is a 25ns UV PLD from the DPLD610 series, featuring a PAL-type architecture. This CMOS device utilizes 16 macrocells with PAL logic, supporting up to 160 product terms. It offers 20 input lines and 16 I/O lines, accommodating 4 dedicated inputs. The component operates from a 4.75V to 5.25V supply range, with a nominal 5V requirement. Its through-hole, 24-pin ceramic DIP package (JESD-30 code R-GDIP-T24) is suitable for industrial applications. This device is utilized in industrial automation and telecommunications sectors. Propagation delay is rated at 25ns, and the maximum clock frequency is 33.3 MHz.
Additional Information
Series: DPLD610RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 32.0700 |
| Width | 7.6200 |
| Technology | CMOS |
| Architecture | PAL-TYPE |
| Additional_Feature | PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS |
| Clock_Frequency_Max | 33.30000 |
| JESD_30_Code | R-GDIP-T24 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 16 |
| Number_of_Inputs | 20 |
| Number_of_Outputs | 16 |
| Number_of_Product_Terms | 160 |
| Number_of_Terminals | 24 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 4 DEDICATED INPUTS, 16 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, GLASS-SEALED |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP24,.3 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Programmable_Logic_Type | UV PLD |
| Propagation_Delay | 25.000 |
| Seated_Height_Max | 5.7200 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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