MG80960MC-20/SM302
RISC Microprocessor, 32-Bit, 20MHz, CMOS, CPGA132Manufacturer: Intel
Categories: Microprocessors
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The Intel MG80960MC-20-SM302 is a 32-bit, 20MHz RISC microprocessor utilizing advanced CMOS technology. This component features a 132-pin Ceramic Pin Grid Array (CPGA) package, specified by JESD-30 code S-CPGA-P132, with a terminal pitch of 2.540mm. It includes integrated cache and supports floating-point operations. Designed for demanding environments, it operates within a temperature range of -55°C to 125°C and requires a supply voltage between 4.75V and 5.25V with a nominal 5V. The MG80960 series is employed in aerospace, defense, and industrial control applications requiring high reliability and robust performance. This specific component adheres to MIL-STD-883 screening levels, ensuring suitability for mission-critical systems.
Additional Information
Series: MG80960RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Format | Floating Point |
| Length | 36.8020 |
| Width | 36.8020 |
| Technology | CMOS |
| Speed | 20.00000000 |
| Additional_Feature | SEATED HT-CALCULATED |
| Address_Bus_Width | 32 |
| Bit_Size | 32 |
| Boundary_Scan | No |
| External_Data_Bus_Width | 32 |
| Integrated_Cache | Yes |
| JESD_30_Code | S-CPGA-P132 |
| Low_Power_Mode | No |
| Number_of_Terminals | 132 |
| Operating_Temperature_Max | 125.0000 |
| Operating_Temperature_Min | -55.0000 |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA132,14X14 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Screening_Level_Reference_Standard | MIL-STD-883 |
| Seated_Height_Max | 4.0610 |
| Supply_Current_Max | 420.00000000 |
| Supply_Voltage_Max | 5.2500 |
| Supply_Voltage_Min | 4.7500 |
| Supply_Voltage_Nom | 5.0000 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
| uPs_uCs_Peripheral_ICs_Type | MICROPROCESSOR, RISC |
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