MPM5130QC-2
Mask PLD, 45ns, CMOS, PQFP100Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
The Altera MPM5130 in the MPM5130 series is a Mask PLD utilizing CMOS technology. This component, part number MPM5130QC-2, offers 128 macrocells with 8 interconnected LABs and a Programmable Interconnect Array (PIA). It supports one external clock input and features 19 dedicated input pins, along with 64 I/O lines. The device has a maximum clock frequency of 40 MHz and a propagation delay of 45 ns. Packaged in a 100-pin PQFP (R-PQFP-G100) with a 0.65 mm terminal pitch, it operates within a temperature range of 0°C to 70°C and a supply voltage of 4.75V to 5.25V. Industries benefiting from this device include telecommunications and industrial control.
Additional Information
Series: MPM5130RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 20.0000 |
| Width | 13.2000 |
| Technology | CMOS |
| Additional_Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| Clock_Frequency_Max | 40.00000 |
| JESD_30_Code | R-PQFP-G100 |
| Number_of_Dedicated_Inputs | 19 |
| Number_of_I_O_Lines | 64 |
| Number_of_Terminals | 100 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 19 DEDICATED INPUTS, 64 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QFP |
| Package_Equivalence_Code | QFP100,.7X.9 |
| Package_Shape | Rectangular |
| Package_Style | FlatPack |
| Programmable_Logic_Type | MASK PLD |
| Propagation_Delay | 45.000 |
| Seated_Height_Max | 3.1300 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | Gull Wing |
| Terminal_Pitch | 0.650 |
| Terminal_Position | QUAD |
Request a Quote
Clients Also Buy
MPM5130QC
Mask PLD, 55ns, CMOS, PQFP100
MPM5130GC
Mask PLD, 55ns, CMOS, CPGA100
MPM5130GC-2
Mask PLD, 45ns, CMOS, CPGA100