EPM9560GC280-12
EE PLD, 13.4ns, CMOS, CPGA280Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM9560GC280-12 is an EE PLD from the EPM9560 series, featuring a 13.4ns propagation delay and CMOS technology. This device offers 772 flip-flops and 216 I/O lines, supporting configurable I/O operation with 3.3V or 5V signaling. It operates within a temperature range of 0°C to 70°C and requires a supply voltage of 4.75V to 5.25V. The component is housed in a 280-terminal ceramic, metal-sealed cofired pin grid array (CPGA) package, with a terminal pitch of 2.54mm. Its organization includes 0 dedicated inputs and 216 I/O, with macrocell output functions. This PLD is suitable for applications in telecommunications, industrial control, and consumer electronics.
Additional Information
Series: EPM9560RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 49.7800 |
| Width | 49.7800 |
| Technology | CMOS |
| Additional_Feature | 772 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 125.00000 |
| JESD_30_Code | S-CPGA-P280 |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 216 |
| Number_of_Terminals | 280 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 216 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA280,19X19 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 13.400 |
| Seated_Height_Max | 5.0810 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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