EPM9480GC280-15
EE PLD, 16.4ns, 480-Cell, CMOS, CPGA280Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM9480 series EE PLD, part number EPM9480GC280-15. This device features 480 macrocells and 196 configurable I/O lines supporting 3.3V or 5V operation. With a maximum clock frequency of 117.6 MHz and a propagation delay of 16.4 ns, it utilizes CMOS technology. The component is housed in a 280-terminal Ceramic Pin Grid Array (CPGA) package (JESD-30 Code: S-CPGA-P280). In-system programmable and equipped with JTAG Boundary Scan Test (BST) capabilities. Typical applications include industrial automation, telecommunications infrastructure, and consumer electronics requiring flexible logic implementation. The operating temperature range is 0°C to 70°C with a nominal supply voltage of 5V.
Additional Information
Series: EPM9480RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 49.7800 |
| Width | 49.7800 |
| Technology | CMOS |
| Additional_Feature | 480 MACROCELLS; 676 FLIP FLOPS CONFIGURABLE I/O OPERATION (3.3V OR 5V) |
| Clock_Frequency_Max | 117.60000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-CPGA-P280 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 196 |
| Number_of_Macro_Cells | 480 |
| Number_of_Terminals | 280 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 196 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA280,19X19 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 16.400 |
| Seated_Height_Max | 5.0810 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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