EPM9400GC280-20
EE PLD, 23.2ns, 400-Cell, CMOS, CPGA280Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM9400 Series EE PLD, part number EPM9400GC280-20, offers 400 macrocells and 580 configurable flip-flops within a 280-pin ceramic grid array (CPGA) package. This CMOS device features a maximum clock frequency of 100 MHz and a typical propagation delay of 23.2 ns. It supports configurable I/O operation at 3.3V or 5V, with a supply voltage range of 4.75V to 5.25V. The EPM9400GC280-20 includes 180 I/O lines and is in-system programmable with JTAG boundary scan support. Its durable ceramic, metal-sealed cofired construction makes it suitable for applications in industrial automation, telecommunications, and consumer electronics where robust performance and programmability are essential.
Additional Information
Series: EPM9400RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 49.7800 |
| Width | 49.7800 |
| Technology | CMOS |
| Additional_Feature | 400 MACROCELLS; 580 FLIP FLOPS CONFIGURABLE I/O OPERATION (3.3V OR 5V) |
| Clock_Frequency_Max | 100.00000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-CPGA-P280 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 180 |
| Number_of_Macro_Cells | 400 |
| Number_of_Terminals | 280 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 180 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA280,19X19 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 23.200 |
| Seated_Height_Max | 5.0810 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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