EPM9320GI280-12
EE PLD, 12ns, CMOS, CPGA280Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM9320GI280-12 is an EE PLD featuring 320 macrocells and 484 flip-flops, built on CMOS technology. This device offers configurable I/O operation at either 3.3V or 5V, with a maximum clock frequency of 118 MHz and a propagation delay of 12 ns. It provides 168 I/O lines within a 280-pin Ceramic Metal-Sealed Cofired PGA (Grid Array) package. Operating across a temperature range of -40°C to +85°C, the EPM9320 series is suitable for applications in industrial automation, telecommunications infrastructure, and consumer electronics requiring flexible logic implementation. The device operates with a nominal supply voltage of 5V, ranging from 4.5V to 5.5V.
Additional Information
Series: EPM9320RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 49.7800 |
| Width | 49.7800 |
| Technology | CMOS |
| Additional_Feature | 320 MACROCELLS; 484 FLIP FLOPS; CONFIGURABLE I/O OPERATION - 3.3V OR 5V |
| Clock_Frequency_Max | 118.00000 |
| JESD_30_Code | S-CPGA-P280 |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 168 |
| Number_of_Terminals | 280 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 0 DEDICATED INPUTS, 168 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA280,19X19 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 12.000 |
| Seated_Height_Max | 5.0810 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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