EPM9320GC280-12
EE PLD, 12.8ns, 320-Cell, CMOS, CPGA280Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM9320GC280-12 is an Electrically Erasable Programmable Logic Device from the EPM9320 series. This CMOS device features 320 macrocells and offers 168 user I/O lines, supporting configurable I/O operation at 3.3V or 5V. With a maximum clock frequency of 125 MHz and a propagation delay of 12.8 ns, it is designed for high-performance applications. This in-system programmable device includes JTAG Boundary Scan Test (BST) capability. The component is housed in a 280-pin Ceramic Pin Grid Array (CPGA) package, specified for operation between 0°C and 70°C. Industries served include industrial control, telecommunications, and consumer electronics.
Additional Information
Series: EPM9320RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 49.7800 |
| Technology | CMOS |
| Length | 49.7800 |
| Additional_Feature | 484 FLIP FLOPS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 125.00000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-CPGA-P280 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 168 |
| Number_of_Macro_Cells | 320 |
| Number_of_Terminals | 280 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 168 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA280,19X19 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 12.800 |
| Seated_Height_Max | 5.0810 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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