EPM7384AEQC208-7
EE PLD, 7.5ns, 384-Cell, CMOS, PQFP208Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7384AEQC208-7 is an EE PLD from the EPM7384 series. This device features 384 macrocells and a maximum clock frequency of 166.7 MHz, with a typical propagation delay of 7.5 ns. It is designed with CMOS technology and operates within a supply voltage range of 3.0V to 3.6V. The component is housed in a 208-pin PQFP package (JESD-30 Code: S-PQFP-G208) with a 0.5mm terminal pitch, supporting 176 I/O lines. This in-system programmable device includes JTAG Boundary Scan Test (BST) support. Applications for this device span industrial control systems and telecommunications infrastructure.
Additional Information
Series: EPM7384RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 28.0000 |
| Technology | CMOS |
| Length | 28.0000 |
| Additional_Feature | 384 MACROCELLS |
| Clock_Frequency_Max | 166.70000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PQFP-G208 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 176 |
| Number_of_Macro_Cells | 384 |
| Number_of_Terminals | 208 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 176 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | FQFP |
| Package_Equivalence_Code | QFP208,1.2SQ,20 |
| Package_Shape | Square |
| Package_Style | FLATPACK, FINE PITCH |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 7.500 |
| Seated_Height_Max | 4.1000 |
| Supply_Voltage_Max | 3.60000 |
| Supply_Voltage_Min | 3.00000 |
| Supply_Voltage_Nom | 3.3 |
| Surface_Mount | Yes |
| Terminal_Form | Gull Wing |
| Terminal_Pitch | 0.500 |
| Terminal_Position | QUAD |
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