EPM7256SQI208-7
EE PLD, 7.5ns, 256-Cell, CMOS, PQFP208Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM7256 EE PLD, part number EPM7256SQI208-7, offers 256 macrocells and a 7.5ns propagation delay. This CMOS device operates within a 4.5V to 5.5V supply range, with a nominal 5V requirement. It features 164 I/O lines and a maximum clock frequency of 166.7 MHz. The EPM7256 series is designed for in-system programmability with JTAG Boundary Scan Test (BST) support. Packaged in a 208-lead fine-pitch quad flat pack (PQFP208), it is suitable for surface-mount applications. This component finds application in telecommunications, industrial controls, and computing systems. The operating temperature range is -40°C to +85°C.
Additional Information
Series: EPM7256RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 28.0000 |
| Width | 28.0000 |
| Technology | CMOS |
| Additional_Feature | 256 MACROCELLS |
| Clock_Frequency_Max | 166.70000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PQFP-G208 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 164 |
| Number_of_Inputs | 164 |
| Number_of_Macro_Cells | 256 |
| Number_of_Outputs | 164 |
| Number_of_Terminals | 208 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 0 DEDICATED INPUTS, 164 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | FQFP |
| Package_Equivalence_Code | QFP208,1.2SQ,20 |
| Package_Shape | Square |
| Package_Style | FLATPACK, FINE PITCH |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 7.500 |
| Seated_Height_Max | 4.1000 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | Gull Wing |
| Terminal_Pitch | 0.500 |
| Terminal_Position | QUAD |
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