EPM7256EGC192-12PP
EE PLD, 12ns, CMOS, CPGA192Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7256EGC192-12PP is an EE PLD from the EPM7256 series, featuring a 12ns propagation delay and CMOS technology. This component offers 164 I/O lines and is housed in a 192-terminal Ceramic Pin Grid Array (CPGA) package, specified by JESD-30 Code S-CPGA-P192. It operates within a temperature range of 0°C to 70°C and supports supply voltages from 4.75V to 5.25V. The device is designed for applications requiring flexible logic implementation in areas such as industrial automation, telecommunications, and consumer electronics. Its organization includes macrocells for output functions, providing efficient programmable logic solutions.
Additional Information
Series: EPM7256RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 45.1500 |
| Width | 45.1500 |
| Technology | CMOS |
| Clock_Frequency_Max | 125.00000 |
| JESD_30_Code | S-CPGA-P192 |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 164 |
| Number_of_Terminals | 192 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 164 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 12.000 |
| Seated_Height_Max | 5.4300 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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