EPM7256BFI100-7
EE PLD, 7.5ns, 256-Cell, CMOS, PBGA100Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7256BFI100-7 is an EE PLD featuring 256 macrocells and an organization of 4 dedicated inputs and 84 I/O lines. This CMOS device operates with a propagation delay of 7.5 ns and a maximum clock frequency of 126.6 MHz. It is in-system programmable and supports JTAG boundary scan testing. The component is housed in a 100-terminal PBGA package (JESD-30 code S-PBGA-B100) with a terminal pitch of 1.000 mm, measuring 11x11 mm. Typical applications include industrial automation, telecommunications, and consumer electronics. The supply voltage range is from 2.375V to 2.625V, with a nominal voltage of 2.5V.
Additional Information
Series: EPM7256RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 11.0000 |
| Width | 11.0000 |
| Technology | CMOS |
| Additional_Feature | Yes |
| Clock_Frequency_Max | 126.60000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PBGA-B100 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 84 |
| Number_of_Macro_Cells | 256 |
| Number_of_Terminals | 100 |
| Organization | 4 DEDICATED INPUTS, 84 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | LBGA |
| Package_Equivalence_Code | BGA100,10X10,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, LOW PROFILE |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 7.500 |
| Seated_Height_Max | 1.7000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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