EPM7256BFI100-10
EE PLD, 10ns, 256-Cell, CMOS, PBGA100Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM7256BFI100-10 is an EE PLD from the EPM7256 series, featuring 256 macrocells and a 10ns propagation delay. This CMOS device operates with a nominal supply voltage of 2.5V, with a range of 2.375V to 2.625V. It offers 84 I/O lines and 4 dedicated inputs, housed in a 100-terminal PBGA (Plastic Ball Grid Array) package with a 1.000mm terminal pitch. The EPM7256BFI100-10 supports in-system programming and JTAG Boundary Scan Test (BST). Its maximum clock frequency is 95.20000 MHz. This component finds application in industrial automation, telecommunications, and consumer electronics sectors.
Additional Information
Series: EPM7256RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 11.0000 |
| Width | 11.0000 |
| Technology | CMOS |
| Additional_Feature | Yes |
| Clock_Frequency_Max | 95.20000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PBGA-B100 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 84 |
| Number_of_Macro_Cells | 256 |
| Number_of_Terminals | 100 |
| Organization | 4 DEDICATED INPUTS, 84 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | LBGA |
| Package_Equivalence_Code | BGA100,10X10,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, LOW PROFILE |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 10.000 |
| Seated_Height_Max | 1.7000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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