EPM7096LC68-10H
EE PLD, 10ns, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
The Altera EPM7096LC68-10H is an EE PLD from the EPM7096 series, utilizing CMOS technology. This device features a maximum clock frequency of 125 MHz and a propagation delay of 10 ns. It offers 52 I/O lines within a 68-terminal PQCC68 package, designed for surface mounting with a terminal pitch of 1.270 mm. The operating supply voltage ranges from 4.75V to 5.25V. This component is suitable for applications in industrial automation, telecommunications, and consumer electronics.
Additional Information
Series: EPM7096RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.2316 |
| Width | 24.2316 |
| Technology | CMOS |
| Clock_Frequency_Max | 125.00000 |
| JESD_30_Code | S-PQCC-J68 |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 52 |
| Number_of_Inputs | 52 |
| Number_of_Outputs | 52 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 52 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 10.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
Request a Quote
Clients Also Buy
EPM7096STC100-7
EE PLD, 7.5ns, 96-Cell, CMOS, PQFP100
EPM7096SQC100-7C
EE PLD, 7.5ns, CMOS, PQFP100
EPM7096QC100-12C
EE PLD, 12ns, CMOS, PQFP100