EPM7096JC68-3
EE PLD, 20ns, 96-Cell, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The EPM7096JC68-3 from Altera is an EE PLD featuring 96 macrocells and a propagation delay of 20ns. This CMOS device operates with a supply voltage range of 4.75V to 5.25V and supports 48 I/O lines. Designed for surface mounting, it comes in a 68-terminal PQCC package (JESD-30 Code: S-PQCC-J68). The EPM7096 series is suitable for applications in industrial control, telecommunications infrastructure, and consumer electronics, where flexible logic implementation is required.
Additional Information
Series: EPM7096RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 24.2316 |
| Technology | CMOS |
| Length | 24.2316 |
| Additional_Feature | No |
| Clock_Frequency_Max | 62.50000 |
| In_System_Programmable | No |
| JESD_30_Code | S-PQCC-J68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 48 |
| Number_of_Inputs | 52 |
| Number_of_Macro_Cells | 96 |
| Number_of_Outputs | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 20.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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