EPM7064SLC68-7
EE PLD, 7.5ns, 64-Cell, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7064SLC68-7 is a 7.5ns EE PLD from the EPM7064 series, featuring 64 macrocells and a CMOS technology. This device offers configurable I/O operation supporting both 3.3V and 5V logic, with a maximum clock frequency of 125 MHz. It provides 48 I/O lines and operates within a temperature range of 0°C to 70°C, supplied by a nominal 5V with a maximum of 5.25V. Packaged in a J-leaded square chip carrier (PQCC68) with a terminal pitch of 1.27mm, this surface-mount component is suitable for applications in industrial automation, telecommunications, and consumer electronics. The device is in-system programmable, facilitating design iteration and field updates.
Additional Information
Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 24.2300 |
| Technology | CMOS |
| Length | 24.2300 |
| Additional_Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 125.00000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PQCC-J68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 48 |
| Number_of_Macro_Cells | 64 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 7.500 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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