EPM7064SLC68-15
EE PLD, 15ns, 64-Cell, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM7064 series EE PLD, part number EPM7064SLC68-15, offers 64 macrocells and 48 I/O lines within a 15ns propagation delay. This CMOS device operates from a 4.75V to 5.25V supply and features configurable I/O operation supporting 3.3V or 5V logic levels. Designed for in-system programmability, it is housed in a 68-terminal J-bend PQCC package (JESD-30 code S-PQCC-J68). The maximum clock frequency is 76.90000 MHz, with an operating temperature range of 0.0°C to 70.0°C. Applications include industrial automation, telecommunications, and consumer electronics.
Additional Information
Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.2300 |
| Width | 24.2300 |
| Technology | CMOS |
| Additional_Feature | CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 76.90000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PQCC-J68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 48 |
| Number_of_Inputs | 52 |
| Number_of_Macro_Cells | 64 |
| Number_of_Outputs | 48 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 15.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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