EPM7064LI68-12
EE PLD, 12ns, 64-Cell, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7064LI68-12 is a complex programmable logic device (CPLD) from the EPM7064 series. This EE PLD features 64 macrocells and a propagation delay of 12ns, supporting a maximum clock frequency of 125MHz. It operates with a supply voltage range of 4.5V to 5.5V and utilizes CMOS technology. The device offers 52 I/O lines within a 68-terminal PQCC68 package, identified by the JESD-30 code S-PQCC-J68. This component is suitable for applications in telecommunications, industrial control, and consumer electronics, where flexible logic implementation and high-speed performance are critical. It is surface-mountable with J-bend terminals on a 1.270mm pitch. The operating temperature range is -40°C to +85°C.
Additional Information
Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.2316 |
| Width | 24.2316 |
| Technology | CMOS |
| Additional_Feature | 64 MACROCELLS |
| Clock_Frequency_Max | 125.00000 |
| In_System_Programmable | No |
| JESD_30_Code | S-PQCC-J68 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 52 |
| Number_of_Inputs | 52 |
| Number_of_Macro_Cells | 64 |
| Number_of_Outputs | 52 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 0 DEDICATED INPUTS, 52 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 12.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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