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EPM7064LI68-12

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EPM7064LI68-12

EE PLD, 12ns, 64-Cell, CMOS, PQCC68

Manufacturer: Altera

Categories: Programmable Logic Devices

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The Altera EPM7064LI68-12 is a complex programmable logic device (CPLD) from the EPM7064 series. This EE PLD features 64 macrocells and a propagation delay of 12ns, supporting a maximum clock frequency of 125MHz. It operates with a supply voltage range of 4.5V to 5.5V and utilizes CMOS technology. The device offers 52 I/O lines within a 68-terminal PQCC68 package, identified by the JESD-30 code S-PQCC-J68. This component is suitable for applications in telecommunications, industrial control, and consumer electronics, where flexible logic implementation and high-speed performance are critical. It is surface-mountable with J-bend terminals on a 1.270mm pitch. The operating temperature range is -40°C to +85°C.

Additional Information

Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Length24.2316
Width24.2316
TechnologyCMOS
Additional_Feature64 MACROCELLS
Clock_Frequency_Max125.00000
In_System_ProgrammableNo
JESD_30_CodeS-PQCC-J68
JTAG_BSTNo
Number_of_Dedicated_Inputs0
Number_of_I_O_Lines52
Number_of_Inputs52
Number_of_Macro_Cells64
Number_of_Outputs52
Number_of_Terminals68
Operating_Temperature_Max85.0
Operating_Temperature_Min-40.0
Organization0 DEDICATED INPUTS, 52 I/O
Output_FunctionMACROCELL
Package_Body_MaterialPLASTIC/EPOXY
Package_CodeQCCJ
Package_Equivalence_CodeLDCC68,1.0SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER
Programmable_Logic_TypeEE PLD
Propagation_Delay12.000
Seated_Height_Max5.0800
Supply_Voltage_Max5.50000
Supply_Voltage_Min4.50000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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