EPM7064BFC256-7
EE PLD, 7.5ns, 64-Cell, CMOS, PBGA256Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7064BFC256-7 is a CMOS EE PLD from the EPM7064 series. This device features 64 macrocells and offers a propagation delay of 7.5 ns. It supports in-system programming and includes JTAG Boundary Scan Test (BST) functionality. Designed for surface mounting, it utilizes a PBGA256 package with a terminal pitch of 1.000 mm and a body size of 17x17 mm. The device operates within a supply voltage range of 2.375 V to 2.625 V, with a nominal voltage of 2.5 V. With 68 I/O lines and 4 dedicated inputs, it is suitable for applications in industrial automation, telecommunications, and consumer electronics.
Additional Information
Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 17.0000 |
| Width | 17.0000 |
| Technology | CMOS |
| Additional_Feature | Yes |
| Clock_Frequency_Max | 135.10000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PBGA-B256 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 68 |
| Number_of_Macro_Cells | 64 |
| Number_of_Terminals | 256 |
| Organization | 4 DEDICATED INPUTS, 68 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Equivalence_Code | BGA256,16X16,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 7.500 |
| Seated_Height_Max | 2.1000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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