EPM7064BFC256-3
EE PLD, 3.5ns, 64-Cell, CMOS, PBGA256Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM7064BFC256-3 is an EE PLD from the EPM7064 series, featuring 64 macrocells and a propagation delay of 3.5ns. This CMOS device operates with a nominal supply voltage of 2.5V, ranging from 2.375V to 2.625V. It offers 68 I/O lines and 4 dedicated inputs, with an organization of 4 dedicated inputs and 68 I/O. The component is housed in a 256-ball grid array (BGA) package (JESD-30 code S-PBGA-B256) with a 1.000mm terminal pitch, adhering to a square package shape and grid array style. In-system programmability and JTAG Boundary Scan Test (BST) are supported. This device finds application in industrial automation, medical equipment, and telecommunications systems. The maximum clock frequency is 277.80000 MHz.
Additional Information
Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 17.0000 |
| Width | 17.0000 |
| Technology | CMOS |
| Additional_Feature | Yes |
| Clock_Frequency_Max | 277.80000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PBGA-B256 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 68 |
| Number_of_Macro_Cells | 64 |
| Number_of_Terminals | 256 |
| Organization | 4 DEDICATED INPUTS, 68 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Equivalence_Code | BGA256,16X16,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 3.500 |
| Seated_Height_Max | 2.1000 |
| Supply_Voltage_Max | 2.62500 |
| Supply_Voltage_Min | 2.37500 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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