EPM7064AELC84-7
EE PLD, 7.5ns, 64-Cell, CMOS, PQCC84Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM7064AELC84-7 is an EE PLD from the EPM7064 series, featuring 64 macrocells and a propagation delay of 7.5 ns. This CMOS device operates with a nominal supply voltage of 3.3V, ranging from 3.0V to 3.6V, and is housed in an 84-terminal PQCC package (JESD-30 Code: S-PQCC-J84). With 68 I/O lines, this in-system programmable device supports JTAG Boundary Scan Testing (BST). Its typical applications span industrial control, telecommunications, and consumer electronics where flexible logic implementation is required. The maximum operating temperature is 70.0°C.
Additional Information
Series: EPM7064RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 29.3116 |
| Width | 29.3116 |
| Technology | CMOS |
| Additional_Feature | 64 MACROCELLS |
| Clock_Frequency_Max | 166.70000 |
| In_System_Programmable | Yes |
| JESD_30_Code | S-PQCC-J84 |
| JTAG_BST | Yes |
| Number_of_Dedicated_Inputs | 0 |
| Number_of_I_O_Lines | 68 |
| Number_of_Macro_Cells | 64 |
| Number_of_Terminals | 84 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 0 DEDICATED INPUTS, 68 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC84,1.2SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 7.500 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 3.60000 |
| Supply_Voltage_Min | 3.00000 |
| Supply_Voltage_Nom | 3.3 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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