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EPM5130LI-2

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EPM5130LI-2

OT PLD, 45ns, 128-Cell, CMOS, PQCC84

Manufacturer: Altera

Categories: Programmable Logic Devices

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Altera EPM5130 Programmable Logic Device (PLD), part number EPM5130LI-2, offers 128 macrocells within an 8-LAB architecture interconnected by a Programmable Interconnect Array (PIA). This CMOS device features a maximum clock frequency of 40 MHz and a propagation delay of 45 ns. It includes 19 dedicated inputs, 48 I/O lines, and supports 68 total inputs. The EPM5130LI-2 is housed in an 84-terminal PQCC package (JESD-30 Code S-PQCC-J84) with a 1.27mm terminal pitch, suitable for surface mounting. Operating across a temperature range of -40°C to 85°C, it requires a supply voltage between 4.5V and 5.5V. This component is utilized in industrial control, telecommunications, and consumer electronics applications.

Additional Information

Series: EPM5130RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Length29.3116
Width29.3116
TechnologyCMOS
Additional_FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Clock_Frequency_Max40.00000
In_System_ProgrammableNo
JESD_30_CodeS-PQCC-J84
JTAG_BSTNo
Number_of_Dedicated_Inputs19
Number_of_I_O_Lines48
Number_of_Inputs68
Number_of_Macro_Cells128
Number_of_Outputs48
Number_of_Terminals84
Operating_Temperature_Max85.0
Operating_Temperature_Min-40.0
Organization19 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialPLASTIC/EPOXY
Package_CodeQCCJ
Package_Equivalence_CodeLDCC84,1.2SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER
Programmable_Logic_TypeOT PLD
Propagation_Delay45.000
Seated_Height_Max5.0800
Supply_Voltage_Max5.50000
Supply_Voltage_Min4.50000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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