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EPM5130LC-1

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EPM5130LC-1

OT PLD, 40ns, 128-Cell, CMOS, PQCC84

Manufacturer: Altera

Categories: Programmable Logic Devices

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Altera's EPM5130LC-1 is an MAX 7000S series CPLD featuring 128 macrocells and 48 I/O lines. This device utilizes CMOS technology and offers a propagation delay of 40ns, supporting operation up to a maximum clock frequency of 50 MHz. It includes 19 dedicated inputs and a total of 68 inputs. The EPM5130LC-1 is packaged in an 84-terminal PQCC (JESD-30 Code S-PQCC-J84) with a 1.27mm terminal pitch. Operating within a temperature range of 0°C to 70°C, it requires a supply voltage between 4.75V and 5.25V. This component is suitable for applications in industrial automation, telecommunications, and consumer electronics.

Additional Information

Series: EPM5130RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:
Technical Details:
Width29.3116
TechnologyCMOS
Length29.3116
Additional_FeatureLABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK
Clock_Frequency_Max50.00000
In_System_ProgrammableNo
JESD_30_CodeS-PQCC-J84
JTAG_BSTNo
Number_of_Dedicated_Inputs19
Number_of_I_O_Lines48
Number_of_Inputs68
Number_of_Macro_Cells128
Number_of_Outputs48
Number_of_Terminals84
Operating_Temperature_Max70.0
Operating_Temperature_Min0.0
Organization19 DEDICATED INPUTS, 48 I/O
Output_FunctionMACROCELL
Package_Body_MaterialPLASTIC/EPOXY
Package_CodeQCCJ
Package_Equivalence_CodeLDCC84,1.2SQ
Package_ShapeSquare
Package_StyleCHIP CARRIER
Programmable_Logic_TypeOT PLD
Propagation_Delay40.000
Seated_Height_Max5.0800
Supply_Voltage_Max5.25000
Supply_Voltage_Min4.75000
Supply_Voltage_Nom5
Surface_MountYes
Terminal_FormJ BEND
Terminal_Pitch1.270
Terminal_PositionQUAD

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