

Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
| Length | 33.5280 |
| Width | 33.5280 |
| Technology | CMOS |
| Additional_Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 128 MACROCELLS; 1 EXTERNAL CLOCK; SHARED INPUT/CLOCK |
| Clock_Frequency_Max | 50.00000 |
| In_System_Programmable | No |
| JESD_30_Code | S-CPGA-P100 |
| JTAG_BST | No |
| Number_of_Dedicated_Inputs | 19 |
| Number_of_I_O_Lines | 48 |
| Number_of_Inputs | 68 |
| Number_of_Macro_Cells | 128 |
| Number_of_Outputs | 48 |
| Number_of_Terminals | 100 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 19 DEDICATED INPUTS, 48 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Equivalence_Code | PGA100M,13X13 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | UV PLD |
| Propagation_Delay | 40.000 |
| Seated_Height_Max | 3.8100 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |