EPM5128ALI68-20
OT PLD, 33ns, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPM5128 is a 33ns CMOS OT PLD belonging to the EPM5128 series, housed in a 68-pin PQCC package (JESD-30 Code: S-PQCC-J68). This device features 8 interconnectable LABs (Logic Array Blocks) with a Programmable Interconnect Array (PIA) and supports one external clock input. It offers a maximum clock frequency of 66.7 MHz and a propagation delay of 33 ns. The organization includes 7 dedicated inputs and 52 I/O lines, totaling 68 terminals. This surface-mount component operates within a temperature range of -40°C to 85°C and requires a supply voltage between 4.5V and 5.5V. The Altera EPM5128 is suitable for applications in industrial control, telecommunications, and consumer electronics.
Additional Information
Series: EPM5128RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 24.2316 |
| Technology | CMOS |
| Length | 24.2316 |
| Additional_Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 1 EXTERNAL CLOCK |
| Clock_Frequency_Max | 66.70000 |
| JESD_30_Code | S-PQCC-J68 |
| Number_of_Dedicated_Inputs | 7 |
| Number_of_I_O_Lines | 52 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 7 DEDICATED INPUTS, 52 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 33.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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