EPM5128ALC68-12
OT PLD, 20ns, CMOS, PQCC68Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPM5128ALC68-12 is an OT PLD from the EPM5128 series, featuring 8 LABs interconnected by a Programmable Interconnect Array (PIA) and supporting 1 external clock. This CMOS device operates with a supply voltage range of 4.75V to 5.25V and offers a maximum clock frequency of 111.1 MHz. It provides 7 dedicated inputs and 52 I/O lines, with a maximum propagation delay of 20 ns. The component is housed in a 68-terminal square J-lead chip carrier package (PQCC68, JESD-30 Code S-PQCC-J68) with a terminal pitch of 1.27mm. Typical applications include industrial automation and consumer electronics.
Additional Information
Series: EPM5128RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 24.2316 |
| Width | 24.2316 |
| Technology | CMOS |
| Additional_Feature | LABS INTERCONNECTED BY PIA; 8 LABS; 1 EXTERNAL CLOCK |
| Clock_Frequency_Max | 111.10000 |
| JESD_30_Code | S-PQCC-J68 |
| Number_of_Dedicated_Inputs | 7 |
| Number_of_I_O_Lines | 52 |
| Number_of_Terminals | 68 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 7 DEDICATED INPUTS, 52 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC68,1.0SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 20.000 |
| Seated_Height_Max | 5.0800 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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