EPF10K70GC503-3
Loadable PLD, 0.5ns, CMOS, CPGA503Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPF10K70 is a loadable PLD from the EPF10K70 series, featuring 3744 logic elements and configurable I/O operation supporting 3.3V or 5V. This component utilizes CMOS technology and is housed in a 503-terminal Ceramic Pin Grid Array (CPGA) package (JESD-30 Code: S-CPGA-P503). It offers a maximum clock frequency of 54.1 MHz and a propagation delay of 0.5 ns. The organization includes 4 dedicated inputs and 358 I/O lines, with registered output functions. Designed for operation between 0°C and 70°C with a nominal supply voltage of 5V (4.75V to 5.25V), this through-hole component is suitable for applications in telecommunications, industrial control, and computing systems.
Additional Information
Series: EPF10K70RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 57.4000 |
| Technology | CMOS |
| Length | 57.4000 |
| Additional_Feature | 3744 LOGIC ELEMENTS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 54.10000 |
| JESD_30_Code | S-CPGA-P503 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 358 |
| Number_of_Inputs | 358 |
| Number_of_Outputs | 358 |
| Number_of_Terminals | 503 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 4 DEDICATED INPUTS, 358 I/O |
| Output_Function | REGISTERED |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | IPGA |
| Package_Equivalence_Code | SPGA503,43X43 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, INTERSTITIAL PITCH |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 0.500 |
| Seated_Height_Max | 5.0770 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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