EPF10K50QC240-4
Loadable PLD, 21.1ns, CMOS, PQFP240Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPF10K50 series Loadable PLD, part number EPF10K50QC240-4, features 2880 logic elements and 189 I/O lines within a 240-terminal PQFP package. This CMOS device offers a maximum clock frequency of 555.56 MHz and a typical propagation delay of 21.1 ns. It includes built-in JTAG boundary-scan test circuitry and operates with a supply voltage range of 4.75V to 5.25V. The EPF10K50QC240-4 is suitable for applications in industrial automation, telecommunications, and consumer electronics. It is designed for surface mounting with a 0.5mm terminal pitch.
Additional Information
Series: EPF10K50RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 32.0000 |
| Width | 32.0000 |
| Technology | CMOS |
| Additional_Feature | 2880 LOGIC ELEMENTS; BUILT-IN JTAG BOUNDARY-SCAN TEST CIRCUITRY |
| Clock_Frequency_Max | 555.56000 |
| JESD_30_Code | S-PQFP-G240 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 189 |
| Number_of_Inputs | 193 |
| Number_of_Outputs | 189 |
| Number_of_Terminals | 240 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 4 DEDICATED INPUTS, 189 I/O |
| Output_Function | REGISTERED |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | FQFP |
| Package_Shape | Square |
| Package_Style | FLATPACK, FINE PITCH |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 21.100 |
| Seated_Height_Max | 4.1000 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | Gull Wing |
| Terminal_Pitch | 0.500 |
| Terminal_Position | QUAD |
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