EPF10K50GI403-5
Loadable PLD, 27ns, CMOS, CPGA403Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPF10K50 series loadable PLD, part number EPF10K50GI403-5, offers 2880 logic elements and 310 I/O lines within a 403-pin Ceramic Pin Grid Array (CPGA) package. This CMOS technology device features configurable I/O operation supporting 3.3V or 5V signals, with a maximum clock frequency of 57.8 MHz. The typical propagation delay is 27 ns. Designed for demanding applications, it finds utility in telecommunications, industrial control, and data processing systems. The component operates across a temperature range of -40°C to 85°C with a supply voltage range of 4.5V to 5.5V.
Additional Information
Series: EPF10K50RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 49.7800 |
| Technology | CMOS |
| Length | 49.7800 |
| Additional_Feature | 2880 LOGIC ELEMENTS; CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 57.80000 |
| JESD_30_Code | S-CPGA-P403 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 310 |
| Number_of_Inputs | 310 |
| Number_of_Outputs | 310 |
| Number_of_Terminals | 403 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 4 DEDICATED INPUTS, 310 I/O |
| Output_Function | REGISTERED |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | IPGA |
| Package_Equivalence_Code | SPGA403M,37X37 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, INTERSTITIAL PITCH |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 27.000 |
| Seated_Height_Max | 3.9160 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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