EPF10K50GI403-3
Loadable PLD, 17.2ns, CMOS, CPGA403Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPF10K50GI403-3 is a loadable PLD from the EPF10K50 series, featuring a CMOS technology and packaged in a 403-pin ceramic grid array (CPGA). This component offers 310 I/O lines and 4 dedicated inputs, with a maximum clock frequency of 434.78 MHz. Its propagation delay is rated at 17.2 ns, and it operates within a supply voltage range of 4.75V to 5.25V. The operating temperature spans from -40°C to +85°C, making it suitable for demanding industrial and telecommunications applications. The 403-terminal package is characterized by its square shape and interstitial pitch.
Additional Information
Series: EPF10K50RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 49.7800 |
| Width | 49.7800 |
| Technology | CMOS |
| Clock_Frequency_Max | 434.78000 |
| JESD_30_Code | S-CPGA-P403 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 310 |
| Number_of_Inputs | 314 |
| Number_of_Outputs | 310 |
| Number_of_Terminals | 403 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 4 DEDICATED INPUTS, 310 I/O |
| Output_Function | REGISTERED |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | IPGA |
| Package_Equivalence_Code | SPGA403M,37X37 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY, INTERSTITIAL PITCH |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 17.200 |
| Seated_Height_Max | 5.0260 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Perpendicular |
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