EPF10K50EFC672-1
Loadable PLD, 8.5ns, CMOS, PBGA672Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EPF10K50EFC672-1 is a Loadable PLD from the EPF10K50 series, featuring CMOS technology and a 672-pin PBGA package. This device offers 254 I/O lines and 4 dedicated inputs, with a maximum clock frequency of 1000 MHz. The propagation delay is specified at 8.5 ns. Operating within a temperature range of 0.0°C to 70.0°C, it requires a supply voltage between 2.3V and 2.7V, with a nominal 2.5V. Its 26x26 mm square package has a terminal pitch of 1.000 mm. This component is suitable for applications in telecommunications, industrial control, and high-performance computing.
Additional Information
Series: EPF10K50RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 27.0000 |
| Width | 27.0000 |
| Technology | CMOS |
| Clock_Frequency_Max | 1000.00000 |
| JESD_30_Code | S-PBGA-B672 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 254 |
| Number_of_Inputs | 258 |
| Number_of_Outputs | 254 |
| Number_of_Terminals | 672 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 4 DEDICATED INPUTS, 254 I/O |
| Output_Function | MIXED |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Equivalence_Code | BGA672,26X26,40 |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 8.500 |
| Seated_Height_Max | 2.1000 |
| Supply_Voltage_Max | 2.70000 |
| Supply_Voltage_Min | 2.30000 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
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