EPF10K130EBC484-1
Loadable PLD, 0.6ns, PBGA484Manufacturer: Altera
Categories: Programmable Logic Devices
Quality Control: Learn More
Altera EPF10K130EBC484-1 is a loadable PLD from the EPF10K130 series. This device features 369 I/O lines and 4 dedicated inputs, with a total of 373 input pins and 369 output pins within its 484-terminal PBGA package. It offers a maximum clock frequency of 1000 MHz and a propagation delay of 0.6 ns. Operating within a temperature range of 0°C to 70°C, this PLD supports a nominal supply voltage of 2.5V, with a maximum of 2.7V and a minimum of 2.3V. The square, grid array package has a terminal pitch of 1.000 mm and is designed for surface mounting. This component finds application in telecommunications, industrial automation, and high-performance computing.
Additional Information
Series: EPF10K130RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 23.0000 |
| Width | 23.0000 |
| Clock_Frequency_Max | 1000.00000 |
| JESD_30_Code | S-PBGA-B484 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 369 |
| Number_of_Inputs | 373 |
| Number_of_Outputs | 369 |
| Number_of_Terminals | 484 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 4 DEDICATED INPUTS, 369 I/O |
| Output_Function | MIXED |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | BGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 0.600 |
| Seated_Height_Max | 1.8600 |
| Supply_Voltage_Max | 2.70000 |
| Supply_Voltage_Min | 2.30000 |
| Supply_Voltage_Nom | 2.5 |
| Surface_Mount | Yes |
| Terminal_Form | Ball |
| Terminal_Pitch | 1.000 |
| Terminal_Position | Bottom |
Request a Quote
Clients Also Buy
EPF10K130EBI356-2X
Loadable PLD, 0.5ns, CMOS, PBGA356
EPF10K130EFC672-1N
Loadable PLD, 0.3ns, CMOS, PBGA672
EPF10K130EFC672-3N
Loadable PLD, 0.6ns, CMOS, PBGA672