EPF10K100GI504-5
Loadable PLD, 27ns, CMOS, CPGA504Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EPF10K100 series loadable PLD, part number EPF10K100GI504-5. This CMOS device features 4992 configurable logic elements and supports configurable I/O operation with 3.3V or 5V tolerance, featuring 406 I/O lines. It operates with a maximum clock frequency of 53.76 MHz and a typical propagation delay of 27 ns. The device is housed in a 504-terminal Ceramic Pin Grid Array (CPGA) package with a terminal pitch of 1.270 mm. Operating temperature range is -40°C to +85°C, with a supply voltage range of 4.5V to 5.5V. Applications include telecommunications, industrial control, and high-performance computing.
Additional Information
Series: EPF10K100RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 57.4000 |
| Width | 57.4000 |
| Technology | CMOS |
| Additional_Feature | 4992 LOGIC ELEMENTS CONFIGURABLE I/O OPERATION WITH 3.3V OR 5V |
| Clock_Frequency_Max | 53.76000 |
| JESD_30_Code | S-CPGA-P504 |
| Number_of_Dedicated_Inputs | 4 |
| Number_of_I_O_Lines | 406 |
| Number_of_Inputs | 410 |
| Number_of_Outputs | 410 |
| Number_of_Terminals | 504 |
| Operating_Temperature_Max | 85.0 |
| Operating_Temperature_Min | -40.0 |
| Organization | 4 DEDICATED INPUTS, 406 I/O |
| Output_Function | REGISTERED |
| Package_Body_Material | CERAMIC, METAL-SEALED COFIRED |
| Package_Code | PGA |
| Package_Shape | Square |
| Package_Style | GRID ARRAY |
| Programmable_Logic_Type | LOADABLE PLD |
| Propagation_Delay | 27.000 |
| Seated_Height_Max | 5.0770 |
| Supply_Voltage_Max | 5.50000 |
| Supply_Voltage_Min | 4.50000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | PIN/PEG |
| Terminal_Pitch | 1.270 |
| Terminal_Position | Perpendicular |
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