EP910IPC40-25
OT PLD, 25ns, PAL-Type, CMOS, PDIP40Manufacturer: Altera
Categories: Programmable Logic Devices
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Altera EP910 Series OT PLD, part number EP910IPC40-25, offers a CMOS PAL-type architecture with 24 macrocells and 2 external clocks. This through-hole component features a 25ns propagation delay and 240 product terms. With 36 total inputs, including 12 dedicated inputs, and 24 I/O lines, it provides flexible logic implementation. The PDIP40 package (JESD-30 Code R-PDIP-T40) operates within a temperature range of 0°C to 70°C and a supply voltage of 4.75V to 5.25V. This device is suitable for applications in industrial control, telecommunications, and consumer electronics.
Additional Information
Series: EP910RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 52.4256 |
| Width | 15.2400 |
| Technology | CMOS |
| Architecture | PAL-TYPE |
| Additional_Feature | 24 MACROCELLS; 2 EXTERNAL CLOCKS |
| Clock_Frequency_Max | 62.50000 |
| JESD_30_Code | R-PDIP-T40 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 24 |
| Number_of_Inputs | 36 |
| Number_of_Outputs | 24 |
| Number_of_Product_Terms | 240 |
| Number_of_Terminals | 40 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 24 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP40,.6 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 25.000 |
| Seated_Height_Max | 4.8260 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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