EP910IPC-12
OT PLD, 15ns, PAL-Type, CMOS, PDIP40Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EP910IPC-12 is an OT PLD from the EP910 series, featuring a PAL-type architecture and CMOS technology. This component offers 24 macrocells interconnected by a global bus, with 12 dedicated inputs and 24 I/O lines. It boasts a propagation delay of 15ns and a maximum clock frequency of 76.9 MHz. The device is housed in a 40-pin PDIP package (R-PDIP-T40) with through-hole termination. Designed for operation between 0°C and 70°C, it requires a supply voltage range of 4.75V to 5.25V. The EP910IPC-12 is suitable for applications in industrial control and telecommunications.
Additional Information
Series: EP910RoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Length | 52.4256 |
| Width | 15.2400 |
| Technology | CMOS |
| Architecture | PAL-TYPE |
| Additional_Feature | MACROCELLS INTERCONNECTED BY GLOBAL BUS; 24 MACROCELLS; 2 EXTERNAL CLOCKS |
| Clock_Frequency_Max | 76.90000 |
| JESD_30_Code | R-PDIP-T40 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 24 |
| Number_of_Inputs | 36 |
| Number_of_Outputs | 24 |
| Number_of_Product_Terms | 240 |
| Number_of_Terminals | 40 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 24 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | DIP |
| Package_Equivalence_Code | DIP40,.6 |
| Package_Shape | Rectangular |
| Package_Style | IN-LINE |
| Programmable_Logic_Type | OT PLD |
| Propagation_Delay | 15.000 |
| Seated_Height_Max | 4.8260 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | No |
| Terminal_Form | THROUGH-HOLE |
| Terminal_Pitch | 2.540 |
| Terminal_Position | Dual |
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