EP910ALC44-12
EE PLD, 13ns, CMOS, PQCC44Manufacturer: Altera
Categories: Programmable Logic Devices
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The Altera EP910A is an EE PLD fabricated in CMOS technology, offering 24 macrocells and 12 dedicated inputs within a 44-terminal PQCC package (JESD-30 Code S-PQCC-J44). This device supports 2 external clocks and features a maximum clock frequency of 83.3 MHz, with a propagation delay of 13 ns. It operates from a supply voltage range of 4.75V to 5.25V and is designed for surface mounting. The EP910A series finds application in various industrial and telecommunications systems requiring flexible programmable logic solutions.
Additional Information
Series: EP910ARoHS Status: Manufacturer Lead Time: Product Status: DiscontinuedPackaging: Datasheet:Download Free CAD Model:
Technical Details:
| Width | 16.5862 |
| Technology | CMOS |
| Length | 16.5862 |
| Additional_Feature | 24 MACROCELLS; 2 EXTERNAL CLOCKS |
| Clock_Frequency_Max | 83.30000 |
| JESD_30_Code | S-PQCC-J44 |
| Number_of_Dedicated_Inputs | 12 |
| Number_of_I_O_Lines | 24 |
| Number_of_Terminals | 44 |
| Operating_Temperature_Max | 70.0 |
| Operating_Temperature_Min | 0.0 |
| Organization | 12 DEDICATED INPUTS, 24 I/O |
| Output_Function | MACROCELL |
| Package_Body_Material | PLASTIC/EPOXY |
| Package_Code | QCCJ |
| Package_Equivalence_Code | LDCC44,.7SQ |
| Package_Shape | Square |
| Package_Style | CHIP CARRIER |
| Programmable_Logic_Type | EE PLD |
| Propagation_Delay | 13.000 |
| Seated_Height_Max | 4.5720 |
| Supply_Voltage_Max | 5.25000 |
| Supply_Voltage_Min | 4.75000 |
| Supply_Voltage_Nom | 5 |
| Surface_Mount | Yes |
| Terminal_Form | J BEND |
| Terminal_Pitch | 1.270 |
| Terminal_Position | QUAD |
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